A step towards smaller, more energy-efficient CMOS devices

A multiplier is an essential component of a digital system. In an article recently published in Electronics Letters, the researchers built an ultra-efficient, less complicated and high-speed simple multiplier based on the mathematics of the two-bit Vedic multiplier using a QCADesigner-E modeling environment. The proposed architecture has less area and number of cells than other current structures.

​​​​​​​Study: A novel nanoscale architecture of the Vedic multiplier using majority logic in quantum dot cellular automata technology. Image Credit: GiroScience/Shutterstock.com

Quantum dot cellular automata (QCA)

Nanoscience and nanoparticles have gained popularity in recent years. At the nanoscale, current transistor-based technologies exhibit physical constraints, causing the characteristics of field-effect transistors to degrade, thus producing short channel effect difficulties. To this end, substituted nanotechnologies such as nanowire transistors, sin electron transistors and QCA can overcome these shortcomings.

While transistor-based technology uses voltage levels, QCA uses the free electron position of the cell, suggesting the importance of cells in QCA technology which is used in data transfer, connectivity or computing logic. Based on recent improvements, QCA circuits can achieve room temperature operation, high density, and fast switching speeds. Additionally, incorporating a multi-layer crossover design into QCA circuits can reduce cell count, space, and circuit complexity.

Vedic multiplier based on QCA

In the present study, the authors adopted a multi-layered architecture. They suggested a half-adder design with a combination of majority gates and inverter in QCA. Additionally, a Vedic multiplication allowed for bitwise multiplication, column-level additions, and addition of products. The recommended circuit includes four AND gates and two half-adders.

Due to the low complexity of the structure of the half adders, the 2×2 Vedic multipliers were applied as a low complexity multi-layer design using QCADesigner-E with majority gates. The suggested QCA-based Vedic multiplier had 115 cells, which required four clock phases. Thus, the suggested architecture had a reduced area and number of cells compared to other current structures. Moreover, the results of the simulation studies revealed the long-term viability of the suggested design, which can be applied to the construction of complicated circuits for nano-communication networks.

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The Vedic multiplier was developed using majority gates, which offered new half-adder designs. These designs were equation-based structures, combining majority gates and a mixture of inverters.

A half subtractor creates the difference and subtracts two binary bits, X and Y, for borrowing. An overflow in a multi-digit subtraction is represented as a borrow signal. If the subtraction is performed by borrowing a ‘1’, the borrowing output is indicated as an AND, where XOR and an inverter have been applied to build the half-subtractor circuit. The inputs of the XOR gates included the output of the AND gate. The design for this experiment consisted of cells in an area of ​​0.02 square micrometers, and the output was generated after 0.25 clock phases.

Vedic multiplication helps in product and column addition as well as bitwise multiplications. The partial product was considered the least significant bit (LSB) of the final product after multiplying the LSB of Y (Y0) with that of X (X0), arranged vertically. Moreover, the LSB of Y (Y0) was then multiplied by the most significant bit (MSB) X (X1), and Y (Y1) of MSB was multiplied by X (X0) of LSB, arranged in a cross. A later half adder combined the product (X0 ×Y1+X0 ×Y1) partial products, which produced Z1 and S1 as a two-bit result, in which the S1 of LSB was considered the second bit of the final product, and the Z1 of MSB was kept as a carry forward for the next step. Finally, multiplying Y (Y1) of MSB with X (X1) of MSB resulted in the creation of (X1 ×Y1) partial product, and the half adder added the previously recorded pre-carry. The resulting Z2 and S2 two bits were the third and fourth bits of the product.

The quantum cost, area, delay and throughput of the Vedic multiplier were calculated using the QCA Designer-E. The team used a consistency vector engine and default settings for the simulation. To ensure consistency and proper propagation of data transmission in the suggested design, the team used cells/each clock area as a design parameter.

The simulation results corresponded to the values ​​of the theoretical half adder in the QCA technology, indicating the robustness of the proposed design. The circuit consisted of 16 cells with 0.25 clock phases and an area of ​​0.02 micrometers. The Vedic multiplier in QCA technology usually consists of two half adders and majority gates. However, this experiment included only 115 normal QCA cells. Additionally, power dissipation was evaluated using QCADesigner-E in QCA technology. Therefore, the energy dissipation of the Vedic multiplier circuit was also evaluated using QCADesigner-E.


In conclusion, nanotechnology has led to recent advances in nanoelectronic circuits. Due to its higher speed and lower power consumption, QCA provides a reliable alternative to transistor-based technology. Through this study, researchers reported a strategy to construct Vedic multipliers with cellular interaction QCA structures.

The authors successfully designed and simulated a half adder circuit with a QCADesigner-E modeling environment and built a 2 X 2 Vedic multiplier circuit. The team compared the performance of the suggested component with the other standard designs regarding the area, cell count, latency and quantum cost.


Huang, J. and Lale, S. (2022), A Novel Vedic Multiplier Nanoscale Architecture Using Majority Logic in Quantum Dot Cellular Automaton Technology. Electronic letters.https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/ell2.12552

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